With the fast development of communication and chip technologies, bandwidth requirements for data exchange between chips are greater and greater. However, due to encapsulation limitation and interference between buses, it is impossible to increase the width of a parallel bus unlimitedly to improve signal transmission bandwidth. In this case, a high-speed serial link technology is developed rapidly, where a component implementing serial-parallel conversion and parallel-serial conversion of data is generally referred to as a Serializer and Deserializer (SerDes).
Interlaken is an optimized interconnection protocol to achieve high bandwidth and reliable packet transmission, and the protocol uses multiple SerDes links to establish a logical connection between components and improve the performance of a communication device by using multi-channel, an anti-pressure capability, and data integrity protection. A series of a configurable number of SerDes links may be used in an Interlaken interconnection protocol to transmit data; therefore, the transmission efficiency is high, expansibility and flexibility are strong, and security and reliability are guaranteed. No upper limit is set for the bus capacity in theory and the bus capacity can be adjusted automatically according to user requirements, and therefore, becomes a preferred choice of next generation communications devices.
FIG. 1 is a schematic diagram in which chips are interconnected through an Interlaken interface. The bandwidth of the interface needs to be determined before connection of the chips, and a proper SerDes speed needs to be selected at the same time, thereby determining a proper number of SerDes links. Each SerDes link is a data channel, and data is transmitted on the SerDes links in parallel.
During the implementation of the present invention, the inventors find that, in an actual application, with the continuous increase of the bandwidth of a device, the number of required SerDeses is increased too. The ratio of power consumption of the SerDes in power consumption of all chips is greater and greater, especially for a router product. The data traffic change in each time segment is also great, and traffic between chips in many time segments is not half of the bandwidth of an interface. Once data between chips starts to be transmitted, regardless of a change of data traffic between chips, all SerDes links work normally, and the number of links cannot be changed, which results in a great waste of the bandwidth of the interface and a waste of the whole power consumption of the chips.
For the situation, in the prior art, in order to reduce or increase the number of SerDes links in working, data can only be re-transmitted after the data traffic between the chips is interrupted, the interface is re-configured, and the SerDes links are re-synchronized and re-aligned. In the existing solution, not only the data traffic needs to be interrupted, but also time required for re-synchronization and re-alignment is long.